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- Design a 16-bit full adder using Verilog entry and test the adder using the following hexadecimal values as input by using Modelsim: [15:0] A АВВА FFFF 109E АBCD 0000 [15:0] B ВАВА FFFF 6D99 CDAB 0180 Cin 1 1 [15:0] Sum CoutWrite hamming code for the data 1100 for the (i) Even parity (ii) Odd parity. Explain the process brieflyQ2: Use a Karnaugh map to simplify the following standard SOP expression: XYZ + XYZ + XYZ + XYZ + XYZ + XYZ 101 010 100
- For 8421 to Ex-3 code conversion, X =The 1's complement can be easily obtained by using: * Comparator Subtractor Inverter Adder Add the two BCD numbers: 1001 + 0100 = ? 01010000 00010011 10101111 00101011 The (r-1)'s complement is also called as Diminished radix complement Radix complement None of the abovePlease trace the calculation A-B on a 4-bit two’s complement adder/subtractor. Fill out the tables below. where. A=7, B=6 PLEASE SHOW ALL STEPS IN WRITING . 3 2 1 0 A B C S M V
- Explain the concept of a biased exponent and how it could be useful.Multiply the operands x=- 101*2^(-7) and y=-21*2^(-6) using the booth method. Represent their values in binary, use the booth method to multiply them, represent the result in decimal.Q6: - binary number (e.g., 101 → 100. Also, 000 → 111): a) Show the truth table. b) Show the Boolean expressions for the outputs in SoP. c) Design an efficient circuit using NAND gates only. Design a 3-bit DECrementor, that is, the cicuit generates the previous number of the input
- on on on on A 4-bit carry look-ahead adder and a 64-bit carry look-ahead adder have the same complexity Select one: O True O False Select the correct answer of the BCD addition of: 205+147 Select one: O a. 001101010010 O b. 110001110101 O c. 100111110101 O d. 100001111101 Verilog is a hardware descriptive language that is easier than VHDL. Select one: O True O False In VHDL, a signal's name can only start and contain characters. Select one: O True O FalseUsing full-adders, implement the following function: = X + Y (X and Y are 3-bit numbers)Find the output function of each truth table: (a) As the sum of minterms (b) As the product of maxterms XYZ F 000 1 001 0 010 0 011 1 100 0 101 1 110 0 111 1 ABCD F 0000 1 0001 0 0010 1 0011 1 0100 0 0101 1 0110 1 0111 1 1000 1 1001 1 1010 0 1011 0 1100 0 1101 1 1110 1 1111 1