Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15
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4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5
ADD X3, X1, X2
ADDI X4, X1, #15
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- ILP (Instruction Level Parallelism) processors have the same execution hardware as RISC (Reduced Instruction Set Architecture) processors. The machines without ILP have complex hardware which is hard to implement. A typical ILP allows multiple-cycle operations to be pipelined.Suppose, 4 operations can be carried out in single clock cycle. So there will be 4 functional units, each attached to one of the operations, branch unit, and common register file in the ILP execution hardware. The sub-operations that can be performed by the functional units are Integer ALU, Integer Multiplication, Floating Point Operations, Load, Store. Let the respective latencies be 1, 2, 3, 2, 1.. Let the sequence of instructions be 1. y1 = x1*1010 2. y2 = x2*1100 3. z1 = y1+0010 4. z2 = y2+0101 5. t1 = t1+1 6. p = q*1000 7. clr = clr+0010 8. r = r+0001 Compare with a table, the Sequential record of execution vs. Instruction-level Parallel record of execution Explain your tableQ2. Refer to datapath design on slide no. 26 with added blocks for jump instructions as shown inslide 33 in Chapter 4 (part 1). Let’s assume a program has 500 instructions. These instructions aredistributed as follows:R-Type Immediatearithmetic(addi)Load Store Branch Jump25% 5% 20% 20% 10% 20%Answer the following questions (show calculations):a) How many instructions will use instruction memory?b) How many instructions will use data memory?c) How many instructions will use the sign extend block?d) In the clock cycles, where the sign extend block is not required, does it remain idle? If yes,how? If not, what happens to the output of the block in that cycle? chapter 4, slide 33 is added as an image needed to solve the questionQ1 [8]. Translate this following C code into MIPS instructions. Your translation should be direct, without rearranging instructions to achieve better performance. for(i=0; il=j; i+=2) b[i]=a[i]+ a[i+1]; Assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else. i b C Free R7 R2 R3 j R8 a R1 RO,R10,R11,R12
- lw r1,12(r7)lw r2,16(r7)add r1,r1,r2sw r1,4(r5)a. Identify and describe all the data dependencies.b. How many clock cycles does it take to execute this code without any pipelining?c. How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)?4. The following problems deal with translating from C code to MIPS code or MIPS code to C code. Assume that the signed variables f, g, h and i are assigned to registers $s0, $1, $2, $3 respectively. Assume the base address of the integer arrays A and B are in registers $s4 and $55 respectively. Translate the following MIPS code to C code. Please indicate which elements of integer array A and B are modified by this code. addi $t0, $1, 6 sll $t0, $t0, 4 add $t0, $t0, $5 Iw $t0, 0($t0) sw $t0, 4($4)17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…Translate the following C code into MIPS code. Here X and Y are stored in $s1 and $s2 registers respectively and the base address of A and B are in $s4 and $s5 registers respectively. X = 7* A[6] -4*B[7] Y = 17*(X+A[9]) A[X+1] = Y Please solve this with #proper explanation5. Below is a depiction of a loop in instruction memory address Охо TOP: instruction 1 Ox4 instruction 2 Ox8 instruction 3 OxC instruction 4 Ох10 conditional branch to TOP Assume that the branch target buffer is initially empty, and the prediction bits are set to Strongly Taken (ST). Fill in the blanks On the first pass through the loop we take the branch. The branch target bits are now We suffer stalls. On the second pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the third pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the fourth pass through the loop we don't take the branch. The branch target bits are now We suffer stalls.Recommended textbooks for youDatabase System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSONC How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag…Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill EducationDatabase System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill EducationStarting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSONDigital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSONC How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSONDatabase Systems: Design, Implementation, & Manag…Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage LearningProgrammable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education