Consider a memory-management system based on paging. The total size of the physical memory is 2 GB, laid out over pages of size 8 KB. The logical address space of each process has been limited to 256 MB. a. Determine the total number of bits in the physical address. b. Determine the number of bits specifying page replacement and the number of bits for page frame number. c. Determine the number of page frames. d. Determine the logical address layout.
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- Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? With this system, what’s the maximum number of pages that a process can have? Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number.Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…Consider a system with word-addressable memory in which a word is of 1 byte, 32-bit logical addresses memory, 2 kilobyte page size and page table entries of 4 bytes each. What is the size of the page table in the system in Mega word?
- Consider a logical address space of 1024 pages of 2048 words each, mapped onto a physical memory of 4096 frames. a. How many bits are there in the logical address? b. How many bits are there in the physical address? Show the steps of your solution.Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. Supposed also that each block contains 16 bytes. The size of the offset field is 19 bits and the size of the block field is 0.625 bytes.Consider a computer system with a 30-bit logical address and 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following? Assume that each page table entry is 4 Bytes. c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process. c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels do you need? Draw a figure to show your page systems
- Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 16 bytes: (a) Determine the size of the offset field. (b) Determine the size of the tag field.In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag and offset fields?
- Suppose a computer system uses 16 but addresses for both virtual and physical address. In addition, assume each page (and frame) has a size of 256 bytes. -How many bits are used for page number? -How many bits for offset? -what is the max number of pages a process can have?If we had a computer that can only address data in bytes, but it has fully associative mapping, 16-bit main memory addresses, and 32-bit cache memory blocks. If each block is 16 bytes in size, then...(a) Count the number of bytes in the offset field.The tag field's size in pixels must be calculated (b).Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address?