Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8

Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8

Name: Consider the execution of a program that results in the execution of
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Description: Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHzprocessor. The program consists of four major types of instructions. The instruction mix and the CPI for eachinstruction type are given below. Wh

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q2/ The following program have been executed by an 8085 Microprocessor. Write down the sequence of the process with explain of each step. Address (Hex) 8085 Instruction 5011 LXI B, 11FF 5013 DCX B 5014 MVI B, 00 5015 DCR B 5016 MVI H, A1 5018 INR H
Consider a program containing ‘j’ instructions of which ‘k’ instructions are loop instructions. The program is executed on a system that contains cache. Instruction fetch from memory costs ‘l’ nano-second while that for cache costs ‘m’ nano-second. If loop is executed ‘n’ times and every other instruction is executed once only, a) derive an expression for the speedup due to use of cache (ratio of the program execution time without cache to the program execution time with cache). Assume, cache is empty initially and is large enough to hold the loop completely and all the data required by the program is hard-coded in the program. b) If j = 1500, k = (your registration number), l = 20 nano-seconds , m = 2 nano-seconds, and n = 100 calculate the speedup using your expression derived in ‘a’ part.
Consider a hypothetical computer having instruction length 32 bit and Byte addressable memory. You need to run a program P having 10 Q.4 CO4 instructions 11,12,13...10. All the instructions are stored in consecutive memory locations started from 1000. To run an instruction li, you have to complete four operations: Fetch, Decode, Execute, and Store. The content of Program Counter will be after the completion of fetch operation of instruction 12. There are no jump or branch instruction in program P
5. Below is a depiction of a loop in instruction memory address Охо TOP: instruction 1 Ox4 instruction 2 Ox8 instruction 3 OxC instruction 4 Ох10 conditional branch to TOP Assume that the branch target buffer is initially empty, and the prediction bits are set to Strongly Taken (ST). Fill in the blanks On the first pass through the loop we take the branch. The branch target bits are now We suffer stalls. On the second pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the third pass through the loop we don't take the branch. The branch target bits are now We suffer stalls. On the fourth pass through the loop we don't take the branch. The branch target bits are now We suffer stalls.
Determine the INSTRUCTION TYPE, CONTENT/RESULT of the destination after the execution (if not applicable, NA), the MACHINE CODE, and ADDRESS RANGE when saved in the cs of the given instruction. It will be saved continuously and part of a single program. Instruction type is in SMALL letters. For the machine code, binary is used for the opcode up to the mod reg/RM field but hexadecimal for the displacement and immediate value. Use single space in between bytes. For Address range, registers, and physical memory, use CAPITAL letters. For displacement and immediate values, use CAPITAL letters. Example Answer: Instruction type: data transfer Content of the Destination: AX=12FE (if register) : if memory (lower address first): 12FE0=34,12FE1=12,12FE2=34,12FE3=56 Machine Code: 1001010 10100101 ED FE Address Range: 13ABC-13ABF GIVEN: registers.JPG ... DS = ADEOH DI = 8557H AX = 9267H DX = 6081H %3D CS = BDEAH SI = 57B7H SS = 8998H ВP 3 ВАЕН BX = 7236H IP = 9DCAH %3D %3D СХ 3 САFЕН %3D 1.JPG ...…
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code
Computer Science A[10] = x; Let x is saved in the register ($s0) and the base address of array A is saved in register ($s3). What is the equivalent MIPS instruction of this high-level language?
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%3D Assuming the following address and register contents, determine any four possible ways to put the number 50 into Register P, given the instruction of form MOV P,... for each way. Also describe the type of addressing mode you are using, with suitable diagram. Address Register Location/Name 60 70 80 20 10 Q R U Content 50 20 50 60 80 10 20 10 50 70
In this problem we want to modify the single cycle datapath shown below (also in in slide #1 of "chapter3_single_cycle_datapaths.pptx") so that it supports execution of a new instruction called jump register (jr). PC Add Read address Instruction [31:0) Instruction [25:21) Instruction [20:16] Instruction Instruction [15:11] memory (DMUXT RegDst Instruction [15:0] RegWrite Read register 1 Read register 2 Read data 1 Write Read register data 2 Write data Registers 16 Sign- extend Instruction [5:0] 32 Shift left 2/ ALUSrc (OMUXI) ALU Addresult Zero ALU ALU result ALU control ALUOP #copy contents of "rs" register to PC (PC = $rs) PCSrc ( E3X MemWrite Read data Address Data Write memory data MemRead MemtoReg (-MUXO) jr $rs You are allowed to add new control signal(s), wire(s), muxe(s) to support this instruction. First briefly explain the required modifications. Then indicate the value of each control signal (RegDst, RegWrite, ALUSrc, ALUOP, MemRead, Mem Write, MemToReg). You must use "X"…
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