Consider the following cache configuration Cache#1 32 bytes 90% Cache#2 64 bytes 90% Block Size Hit Rate Further assume both caches have single cycle hit times. Memory bus is 16-bytes wide and support interleaved memory access with 01 cycle to send an address to the RAM, 05-cycles latency for each RAM access, and 01 cycle to return data from the RAM Which cache configuration would be better? Need to show your all calculations.

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