Consider the following set of jobs to be scheduled for execution on a single CPU system. Job Arrival Time Size (msec) Priority 10 J1 J2 J3 JĄ J5 J6 2 (Silver) 1 (Gold) 3 (Bronze) 2 (Silver) 3 (Bronze) 1 (Gold) 8 3 10 4 12 1 15 4
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- Draw a Gantt chart showing FCFS scheduling for these jobs and find average waiting time.
- Draw a Gantt chart showing (non-preemptive) SJF schedulingand find average waiting time
- Draw a Gantt chart showing non-preemptive PRIORITY schedulingand find average turn-around time.
- Draw a Gantt chart showing preemptive PRIORITY schedulingand find average waiting time.
- Which of the foregoing scheduling policies provides the lowest waiting time
for this set of jobs? What is the waiting time with this policy?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?Describe the relationship between dynamic multithreading and out-of-order execution in the context of CPU design.
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- Superscalar processor could be a central processor that implements instruction-level correspondence inside one processor. It will execute over one instruction throughout a clock cycle. It at the same time dispatches multiple directions to completely different execution units on the processor. False TrueIn computer architecture, SIMD may refer to the situation where... a) multiple CPU cores can access the same memory concurrently. b) the same operation can be applied to multiple operands with only a single instruction. c) multiple independent instructions can be executed at the same time in the same CPU core. d) multiple independent memory banks show up as a single address space.One machine uses a 2 GHz clock and executes a program with 4 classes of instructions, A, B, C, D. Their respective cycles/instruction are CPIA=3, CPIB=2, CPIC=4, and CPID=2. Another machine has a faster clock of 3.2 GHz, and a different architecture, such that the same classes of instructions have CPIA=2, CPIB=2, CPIC=3, and CPID=2. Both machines execute a program where the frequency of the four classes of instructions is 30% for Class A, 20% for Class B, 10% for Class C and 40% are instructions of Class D. a. How many instructions did each of the machines execute in 10 seconds (assume no overhead)? b. If a program has 10º instructions, which machines finishes first? c. Which machine is more performant? d. Compare the MIPS of the two machines.