ENTITY black box IS PORT (a, b, cin: IN BIT; sl, s2: OUT BIT); END black_box; ARCHITECTURE dataflow OF black_box IS BEGIN sla XOR b XOR cin; s2 <= (a AND b) OR (a AND cin) OR (b AND cin); END dataflow;

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Q6// Draw the block diagram and make a truth table according to this VHDL code.
ENTITY black box IS
PORT (a, b, cin: IN BIT;
sl, s2: OUT BIT);
END black_box;
ARCHITECTURE dataflow OF black_box IS
BEGIN
sla XOR b XOR cin;
$2 <= (a AND b) OR (a AND cin) OR (b AND cin);
END dataflow;
Transcribed Image Text:Q6// Draw the block diagram and make a truth table according to this VHDL code. ENTITY black box IS PORT (a, b, cin: IN BIT; sl, s2: OUT BIT); END black_box; ARCHITECTURE dataflow OF black_box IS BEGIN sla XOR b XOR cin; $2 <= (a AND b) OR (a AND cin) OR (b AND cin); END dataflow;
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