Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD_LOGIC; Q: out STD_LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0)) & Q(5 downto 1); end if; end process; end behavior;

Figure Q7 describes a Linear Feedback Shift Register (LFSR). Draw the equivalent schematic diagram of the system based on an off-the-shelf shift register, clearly showing the number of exclusive-OR gates needed to construct it. LIBRARY ieee; USE ieee.std logic_1164.all; entity lfsr is CLK, RESET: in STD_LOGIC; Q: out STD_LOGIC_VECTOR (5 downto 0) ); port ( end lfsr; architecture behavior of lfsr is begin process (CLK,RESET) begin if RESET='1' then Q <= "000001"; else Q <= ( Q(3) xor Q(2) xor Q(0)) & Q(5 downto 1); end if; end process; end behavior;

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Task: Draw the State Diagram for the Moore Sequence Detector FSM. How many states have the New State diagram? Given VHDL Code for the Moore Sequence Detector FSM: LIBRARY ieee;USE ieee.std logic 1164.all; ENTITY Seq_Detector_Moore ISPORT ( Clock : IN STD_LOGIC ;Resetn : IN STD _LOGIC ;w : IN STD_LOGIC ;z : OUT STD _LOGIC ) ;END Seq_Detector_Moore; ARCHITECTURE Behavior OF Seq_Detector_Moore ISTYPE state _type IS ( A, B, C) ;SIGNAL current _state, next _state : state _type;BEGIN --next state decoderProcess (current_state, w)BEGINCASE current_state IS WHEN A =>IF w = ’1’ THEN next _state <= A ;ELSE next _state <= B ;END IF ; WHEN B =>IF w = ’1’ THEN next _state <= A ;ELSE next _state <= C ;END IF ; WHEN C =>IF w = ’1’ THEN next _state <= A ;ELSE next _state <= C ;END IF ; WHEN OTHERS =>next_state<= A ; -- go back to the initial stateEND CASEEND PROCESS ; --state memory (FFs)PROCESS ( Clock, Resetn )BEGINIF Resetn = ’1’ THENcurrent_state <=…
Task: Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns. Given VHDL code for the Laser Circuit FSM: library ieee;use ieee.std_logic_1164.all; entity LaserTimer isport ( b: in std_logic;x : out std_logic;clk, rst : in std_logic;);end LaserTimer; architecture behavior of LaserTimer istype statetype is(S_Off, S_On1, S_On2, S_On3);signal currentState, nextState:statetype; beginstatereg: process(clk, rst)beginif (rst=’1’) thencurrentstate <= S_Off;elsif (clk=’1’ and clk’event) thencurrentstate <= nextstate;end if;end process; comblogic: process (currentstate, b)begincase currentstate iswhen S_Off =>x <= ‘0’;if (b=’0’) thennextstate <= S_Off;elsenextstate <= S_On1;end if;when S_On1 =>x <= ‘1’;nextstate <= S_On2;when S_On2 =>x <= ‘1’;nextstate <= S_On3;when S_On3 =>x <= ‘1’;nextstate <= S_Off;end case;end process;end behavior;
code your Boolean function in HDL And.hdl: /** * And gate: * out = 1 if (a == 1 and b == 1) * 0 otherwise */ CHIP And { IN a, b; OUT out; PARTS: Nand(a=a, b=b, out=nandAB); Not(in=nandAB, out=out); } Mystery.hdl CHIP Mystery { IN a, b, c, d; OUT out; PARTS: } Not.hdl /** * Not gate: * out = not in */ CHIP Not { IN in; OUT out; PARTS: // Put your code here: Nand(a=in, b=in, out=out); } Or.hdl /** * Or gate: out = 1 if {a==1 or b==1}, 0 otherwise */ CHIP Or { IN a, b; OUT out; PARTS: Not (in=a, out=nota); Not (in=b, out=notb); Nand (a=nota, b=notb, out=out); }
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Student Ivan 6. Simplify the given expression to its SOP form. Draw the logic circuit for the simplified SOP function. [6marks] Y = (A +B) (A + AB)C+ A(B+ C)+ ĀB+ ABC
23&cmid%3D11597 es This course The code given below is a VHDL implementation of: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity design is Port ( A,B : in STD LOGIC; YO,Y1,Y2,Y3 : out STD LOGIC); end design; architecture behavior of design is begin YO <= ((NOT A)and (NOT B)); Yl <= ((NOT A) and B); Y2 <= (A and (NOT B)); Y3 <= (A and B); end behavior; Select one: O a. 4 to 2 encoder O b. None of the options O C.4 to 1 MUX O d. 2 to 4 decoder