For each of the cache modifications that we could perform, select whether it will increase, decrease, have no effect, or have an unknown effect on the parameter. • An unknown effect means that it could either decrease or increase the parameter in question. • No effect also includes marginal or very little effect • When answering for multilevel caching, answer based on the caching system as a whole. Improvement Increase Cache Size (C) Increase Associativity(K) Increase Block Size(b) Use Multilevel Caching Hit Rate [Select] [Select] [Select] [Select] < Cache Access Time [Select] [Select] [Select] [Select] Average Memory Access Time V [Select] V [Select] [Select] [Select] <

For each of the cache modifications that we could perform, select whether it will increase, decrease, have no effect, or have an unknown effect on the parameter. • An unknown effect means that it could either decrease or increase the parameter in question. • No effect also includes marginal or very little effect • When answering for multilevel caching, answer based on the caching system as a whole. Improvement Increase Cache Size (C) Increase Associativity(K) Increase Block Size(b) Use Multilevel Caching Hit Rate [Select] [Select] [Select] [Select] < Cache Access Time [Select] [Select] [Select] [Select] Average Memory Access Time V [Select] V [Select] [Select] [Select] <

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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For each of the following overhead bits, select whether there are these bits per cache, per set, per block, or per value. • Assume the cache is a K-way set associative cache. Valid Bit Dirty Bit Tag Bits Counter if using FIFO replacement policy Counters if using LRU replacement policy Instance Per [Select] Cache Set Block Value Tecret [Select] [Select]
The padding technique is effective to remove false sharing, but it requires consuming more memory in order to fill in the first cache line to enforce y to move to another cache line. If the memory consumption is a concern, what would you suggest as an alternative possible solution the programmer can do to avoid false sharing?
Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hit
“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…
Caching data may improve performance by taking use of "spatial locality" and "temporal locality." Caches employ these two occurrences in many ways.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>
2-Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 42, 180, 46, 185, 189, 3, 181, 43, 6, 189, 65, 190 b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. c. For each of these references, identify the binary address, the tag, and the index given a two way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty d. For each of these…
A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.
If done properly, "spatial locality" and "temporal locality" in a system may boost its performance. Consider the numerous ways caches exploit these two events.
Differentiate between caches that are totally associative and those that are directly mapped.
A performance gain may be achieved by using data that has been cached in order to take advantage of "spatial locality" and "temporal locality." These two occurrences are used in a cache in a wide range of various ways.
In this chapter, you will learn about the four cache replacement policies that have been discussed.