Given a CMOS inverter with the following operation and devices characteristics: pMOS transistor: W/L = 4; mobility = 120 cm²/V*s; threshold voltage = -0.6V nMOS transistor: W/L = 1; mobility = 240 cm² / V*s; threshold voltage = 0.6V 240 nm process; gate oxide capacitance/unit area = 8.6x107 F/cm², VDD = 2.4V a. Calculate Beta, ß, for each transistor? b. What modes/regions of operation are the transistors in when Vin = 0.2V? Calculate the inverter rise and fall times given a load capacitance of 100fF? d. Calculate the average propagation delay of the inverter? C. e. Draw the VTC curve with a VIL of 0.8V and a VIH of 1.4V? Label all significant points. f. Calculate the noise margin?

Given a CMOS inverter with the following operation and devices characteristics: pMOS transistor: W/L = 4; mobility = 120 cm²/Vs; threshold voltage = -0.6V nMOS transistor: W/L = 1; mobility = 240 cm² / Vs; threshold voltage = 0.6V 240 nm process; gate oxide capacitance/unit area = 8.6x107 F/cm², VDD = 2.4V a. Calculate Beta, ß, for each transistor? b. What modes/regions of operation are the transistors in when Vin = 0.2V? Calculate the inverter rise and fall times given a load capacitance of 100fF? d. Calculate the average propagation delay of the inverter? C. e. Draw the VTC curve with a VIL of 0.8V and a VIH of 1.4V? Label all significant points. f. Calculate the noise margin?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 5VE

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