How many multiplexer would be required to make a bus that has 16 interacting components?
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- A common bus in a computer connects 16 source registers (each register is 32 bits) and one memory unit with word size of 32 bits also. If the bus is designed using multiplexers, answer the following: • What is the minimum number of multiplexers required? What is the minimum number of select lines each multiplexer has? If the bus is designed with three-state buffers and decoders, answer the following: • What is the minimum number of three-state buffers required? • What is the minimum number of decoders required? • What is the minimum size of each decodeSuppose a computer system has a common bus system for 8 registers of 16 bits each.The bus is constructed with multiplexers.a. How many selection inputs are there in each multiplexer?b. What size of multiplexers are needed?c. How many multiplexers are there in the bus?d. Draw the block diagram for this computer common bus system design.Address and data buses are demultiplexed in what way?
- If an address bus has to be able to address eight different devices, how many conductors will it need to have? What happens if each of those devices also has to be able to connect with the device that controls the inputs and outputs?How does a bus design deal with data transmission from several computers at once?List the four signals in an SPI bus and describe each one.
- Difference between address bus & data bus is: Select one: a. Address bus is bidirectional while data bus Is unidirectional. b. Data wires are only for data signals. C. None of the options given here. d. Both carry bits in either directions. e. Address bus is only for addressing signals.What is the definition of an extension bus?: Design a hardware circuit by using common bus architecture to implement (the following Register Transfer Languages. P: A1E A2 Q: A2€ A3 R: A4€ A1 S: A3 EA4, A1E4 Where A1, A2, A3, A4 are one bit register
- II. IMPLEMENTATION OF SIMPLE SYSTEMS. Implement the given RTL below using bus connection and multiplexers and/or tri-state buffers. Assume that the given control signals are all mutually exclusive, and all registers are 4-bit wide. You may include additional flip-flop pins if necessary. A: W + Z,V + 1(high) B: X + V,Z + V C: X +W,Y + 0 (low) D: V + Y,W + Y,z-Y E: Y + X,Z + XWrite the concrete RTN and control signals for not and shra signals for a 2-bus architecture.