Q2.A. Complete the behavioral VHDL code to implement the FSM illustrated in the figure below. What is the type of the FSM is it a Mealy or Moore? . 0 . et 2x1 MUX 1, CLK library ieee; use ieee.std_logic_1164.all; mix out

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Q2.A. Complete the behavioral VHDL code to implement the FSM illustrated in the figure below.
What is the type of the FSM is it a Mealy or Moore?
D
0
10 2x1
ALIT
MUX
1₁
mux out
CLK
library ieee;
use ieee.std_logic_1164.all;
entity logic_circuit is
port(x, clk: in std_logic;
f: buffer std_logic);
end entity;
architecture logic_design of Logic Circuit is
signal d, qd_temp, t: std_logic:='0';
signal i0, il, mux_out: std_logic;
signal qt_temp: std_logic;
begin
mux_out <=i0 when x='0' else
il;
Transcribed Image Text:Q2.A. Complete the behavioral VHDL code to implement the FSM illustrated in the figure below. What is the type of the FSM is it a Mealy or Moore? D 0 10 2x1 ALIT MUX 1₁ mux out CLK library ieee; use ieee.std_logic_1164.all; entity logic_circuit is port(x, clk: in std_logic; f: buffer std_logic); end entity; architecture logic_design of Logic Circuit is signal d, qd_temp, t: std_logic:='0'; signal i0, il, mux_out: std_logic; signal qt_temp: std_logic; begin mux_out <=i0 when x='0' else il;
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