Q6: Assume total number of addresses a CPU can manage are 12 bits long. a. What is the maximum size of memory if byte addressable? b. What is the maximum size of memory if word (2-byte long) addressable? If CPU uses left most 2 bits to interleave across RAM chips. How many maximum number of RAM chips it can support. C.

Q6: Assume total number of addresses a CPU can manage are 12 bits long. a. What is the maximum size of memory if byte addressable? b. What is the maximum size of memory if word (2-byte long) addressable? If CPU uses left most 2 bits to interleave across RAM chips. How many maximum number of RAM chips it can support. C.

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter10: Pointers

Section10.1: Addresses And Pointers

Problem 12E

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Similar questions

In the ________, memory addresses consist of a single integer.
Most Intel CPUs use the __________, in which each memory address is represented by two integers.
Suppose the RAM for a certain computer has 256M words, where each word is 16 bits long. a. What is the capacity of this memory expressed in bytes? b. If this RAM is byte addressable, how many bits must an address contain? c. If this RAM is word addressable, how many bits must an address contain?
By assuming that X is the last digit of your student number and 3X is a two digit number, consider memory storage of a 64-bit word stored at memory word 3X in a byte-addressable memory (a) What is the byte address of memory word 3X? (b) What are the byte addresses that memory word 3X spans? (c) Draw the number 0XF1234567890ABCDE stored at word 3X in both big-endian and little-endian machines. Clearly label the byte address corresponding to each data byte value.
Exercise 2: A byte addressable memory has a size of 1024 MBytes. This memory is attached to a direct mapping cache of 32KBytes that contains 1024 lines. a. What is the memory address length? b. What is the block size? c. What is the number of blocks in main memory? d. What is the length in bit of: tag (T), line number (L) and byte number (W)? e. Determine in Hexadecimal the tag (T), line number (L) and byte number (W) of the following Hexadecimal memory address: 000008AE f. What is the block that contains the address 000000DE? g. Which line of the cache can hold the block containing 000000DE?
8Gbx32 ROM element is given. a) Specify the address line and the data number line. b) How many bits is the total storage capacity of the memory? c) The total storage capacity of the memory can be specified in Megabytes.d) If we have two 4Gbx16 ROMs, two 2Gbx16 and 2Gbx32 modules, use these elements to design the 8Gbx32 bit memory unit as block diagrams. Express it in a descriptive way.
By assuming that X is the last digit of your student number and 3X is a two digitnumber, consider memory storage of a 64-bit word stored at memory word 3X ina byte-addressable memory(a) What is the byte address of memory word 3X?(b) What are the byte addresses that memory word 3X spans?(c) Draw the number 0xF1234567890ABCDE stored at word 3X in both big-endianand little-endian machines. Clearly label the byte address corresponding to eachdata byte value.
Assume a 2 byte memory. What are the lowest and highest addresses if memory is byte addressable?
Suppose you have an Intel 8086 Microprocessor which is running at a frequency of 50 MHz. Now what is the maximum number of times it can read a byte of data from the memory in 3 seconds? 12500000 37500000 1250000 3750000 Suppose an Intel 8086 Microprocessor is operating at 8 MHz. Which of the following statements are true? ] The clock cycle is 125 ns | In each bus cycle, the clock remains high for 41.25 ns Data is supplied during the 250 ns to 375 ns period in a bus cycle. While reading, ALE stays high during the 125 ns to 250 ns period in a bus cycle. The Status Bus bits becomes available before 250 ns in a bus cycle.
Addressing Memory Suppose that there are 226 bytes in memory. In binary the lowest address is 00...00, and the highest address is 11...11. a. What is the lowest address (in decimal) if memory is byte addressable? b. What is the highest address (in decimal) if memory is byte addressable? c. Suppose that a word is 16-bits long. What is the lowest address (in decimal) if memory is word addressable? d. Suppose that a word is 16-bits long. What is the highest address (in decimal) if memory is word addressable? e. Suppose that a word is 32-bits long. What is the lowest address (in decimal) if memory is word addressable? f. Suppose that a word is 32-bits long. What is the highest address (in decimal) if memory is word addressable?
5. How many bits are required to address a 4M X 16 main memory if a) main memory is byte addressable? b) main memory is word addressable? 6. How many bits are required to address a 1M X 8 main memory if a) main memory is byte addressable? b) main memory is word addressable?
Assume a CPU with a fixed 32-bit instruction length has the following instruction format:opcode mode [operand1] [operand2] [operand3]The mode encodes the number of operands and each operand’s mode. For instance, one mode indicates three registers, another indicates two registers and an immediate datum, another indicates a main memory reference, etc. Assume there are 94 instructions and 22 modes. Answer the following.a. One mode indicates three registers. How many registers can be referenced in this mode?b. One mode indicates two registers and an immediate datum in two’s complement. Assuming there are 32 registers, what is the largest immediate datum that can be referenced?c. One mode has a destination register and a source memory address (an unsignednumber). Assuming 16 registers, what is the largest memory reference available?d. One mode has two memory addresses, both using base displacement. In both, the basesare stored in index registers and the displacements are specified in the…