A digital counter is a device that generates binary numbers in a specified count sequence. The counter progresses through thespecified sequence of numbers when triggered by an incoming clock waveform, and it advances from one number to the next onlyduring the occurence of a dock puse The counter cycles through the same sequence of numbers continuously so long as there isan incoming dock pulse. You are to buld a 3-bit sync count-down counter, which is a counter that counts down goesthrou tates 111 to 000 and back to 11 to repeat the ethe first step of the design, youFlop inputs a column for each fip-fop input The present stanedesign and should enumerate the count sequence. The next state columns should specnonnext, given the present state. For example,circuit is ina present state of the ne e ina down-count sequence would be aYou should design the FF inputs using the JK FF excitation table which is in Figure 11 Once you had completed the statetransition table, une KSimulate your counter circuit using Logisim to verity the cleast significant bits. Figure 2 shows where the JKfrcomplete the simulation of your circut, use thekunit to produce clock pulse that will trigger the fip-fops in the counter circuitFigure 2 shows where the clock unit can.ound in the toolbar menu 4 Connect the output of the clock pulse generator unit tothe clock inputs of the fip flops in synchronous counter circuit. S. Manualy trigger the FFs by cicking on the clock unit in theto use a positive-edgegered Kfip-flops. infolowsumn for n bit neeate transition table witesent State Next State Fip-the fo-fop's inout as a function of the present state. 2of its operation Un youlabel the most andbe found in the Logisim toolbar menu. 3 Ater you ccessfulysimcircut implementations ir report Extra point For an additional 3 points added to the final exam grade, connect this circut tothe f BCD to 7-ser ant decoder that you may have designed in project 2(This was the bonus part in project 2 You shouldconnect the outs of the three fip flops in project 3 to the three inputs of the BCD to 7-segment decoder (8,C and D in project 2and observe the LED displays a count down from 7 to 0 and back to 7 ater giving continuous puses of the clockJK FF Function table JK FF Excitation table JKOnt Function On On1KO0 a Hold O0ox010 Reset 011X101Set10X111Q. Comp. 11xO Fig. 1 JK FF characteristic tables DOD 0.00 we Tu Grund AT Stander Athen Dhe tro DO SHOP Greuta Fig. 2. JK FFand Clock unit in Logisim toolbar.

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specified sequence of numbers when triggered by an incoming dlock waveform andit advances from one number to the next only during the occurence of a dock pulse The counter cycles through the same sequence of numbers continuously so long as there is an incoming dock pulse. You are to build a 3-bit sync count-down counter, which is a counter that counts down goes throu tates 111 to 000 and back to 111 to repeat the the first step of the design, you Flop inputs ( column for each fip-fop input The present stane design and should enumerate the count sequence. The net state columns should spec o next, given the present state. For example, circuit is ina present state of the ne eina down-count sequence would be a You should design the FF inputs using the JK FF excitation table which is in Figure 11 Once you had completed the state ransition table, use K. Simulate your counter circult using Logisim to verify the com least significant bits. Figure 2 shows where the JK fro unit can be found in the Logisim toolbar menu 3 Aher you ccessfully complete the simuation of your circuit, use the unit to produce clock puise that wil trigger the fip-fops in the counter circut Figure 2 shows where the dock unit can.ound in the toolbar menu 4 Connect the output of the clock pulse generator unit to the clock inputs of the fip flops in synchronous counter circuit.S. Manualy trigger the FFs by clicking on the clock unit in the use a positive-edge-ered K fip-fops. in esent State Next State Fip- tate transition table with the folow umn forn bit nee the fio-fop's input as a function of the present state. 2 label the most and ess of its operation un you y sim circut implementations irr report Extra point For an additional 3 points added to the final eam grade, connect this circut to the fu BCD to 7-ser ant decoder that you may have designed in project 2 (This was the bonus part in project 2 You should connect the ous of the three fip flops in project 3 to the three inputs of the BCD to 7-segment decoder (,C and D in project 2 and observe the LED displays a count down from 7 to 0 and back to 7 JK FF Function table KFF Excitation tableJKOnt Function On On1KO0 a Hoid O0ox010 Reset 011X101Set10X111 giving continuous pulses of the clock