timescale Ins / lps module mainfunction (input a,b, c, output y); assign y-(a&b) | (alc); endmodule timescale Ins / 1ps module testbench; reg a,b,c; mainfunction dt (.a (a), .b(b),.c(c), -y(y)): initial begin a-0; b-0; c%30; #10 if (y!--1) Sdisplay ("y-logic 0"): end endmodule
timescale Ins / lps module mainfunction (input a,b, c, output y); assign y-(a&b) | (alc); endmodule timescale Ins / 1ps module testbench; reg a,b,c; mainfunction dt (.a (a), .b(b),.c(c), -y(y)): initial begin a-0; b-0; c%30; #10 if (y!--1) Sdisplay ("y-logic 0"): end endmodule
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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![System De...
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timescale Ins / 1ps
module mainfunction (input a,b, c, output y):
assign y-(a&b) I (alc);
endmodule
timescale Ins / lps
module testbench;
reg a,b,c;
mainfunction dt (. a (a),.b (b), .c(c),.y(y)):
initial begin
a=0; b=0; c=0; #10
if (y!--1) $display ("y=logic 0");
end
endmodule
Which of the following is true for the two verilog codes above?
I. Behavioral design level is used.
II. Output(y) is equal to logic 1 and the text "y=logic 0" appears in the simulation.
III. The combinational circuit designed in the code includes 3 logic gates.
IV. A net has to be added to the code for the output.
Your answer:
O LJI
O II,IV
I1,IV
W](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F168d23cc-17df-4d5a-8788-f0f5c43091dc%2F0c5fc0fa-9260-4c93-a694-7f232bcef9a4%2Fmpdab4_processed.jpeg&w=3840&q=75)
Transcribed Image Text:System De...
Overview
Plans
Resources
Status and follow-up
Participants
More
timescale Ins / 1ps
module mainfunction (input a,b, c, output y):
assign y-(a&b) I (alc);
endmodule
timescale Ins / lps
module testbench;
reg a,b,c;
mainfunction dt (. a (a),.b (b), .c(c),.y(y)):
initial begin
a=0; b=0; c=0; #10
if (y!--1) $display ("y=logic 0");
end
endmodule
Which of the following is true for the two verilog codes above?
I. Behavioral design level is used.
II. Output(y) is equal to logic 1 and the text "y=logic 0" appears in the simulation.
III. The combinational circuit designed in the code includes 3 logic gates.
IV. A net has to be added to the code for the output.
Your answer:
O LJI
O II,IV
I1,IV
W
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