Suppose a computer having 5 GHz processor with cycle time of 4ns and main memory access time 200ns with CPI is 1 cycle.
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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hitrate. Its main memory has 40 ns access time. What is the computer’s effective access time? If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what isthe computer’s new effective access time? How much of a speedup does the on-chip cache give the computer?Suppose a computer having 5 GHz processor with cycle time of 2ns and main memory access time 50ns with CPI is 1 cycle. Calculate the processor performance without cache. Calculate the performance with L1 cache, assume L1 hit rate is 92% and access time is 0.2ns. Calculate the performance with L2 cache, assume L2 hit rate is 85% and access time is 0.1ns. Calculate the performance with L3 cache, assume L3 hit rate is 78% and access time is 0.1ns.
- Suppose a computer having 5 GHz processor with cycle time of 4ns and main memory access time 200ns with CPI is 1 cycle. Calculate the processor performance without cache. Calculate the performance with L1 cache, assume L1 hit rate is 85% and access time is 0.4ns. iii. Calculate the performance with L2 cache, assume L2 hit rate is 80% and access time is 10ns. Calculate the performance with L3 cache, assume L3 hit rate is 75% and access time is 10ns.Given a system with separate instruction and data caches, suppose the frequency of data operations is 0.31. Given a HitTime of 1ns for each cache and a miss penalty of 50ns for each cache, calculate the average memory access time (in nsec). Assume that the miss rate for the data cache is 0.08 and the miss rate for the instruction cache is 0.04.Round your answer to two decimal placesA given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hitrate. Its main memory has 40 ns access time.i. What is the computer’s effective access time? ii. If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what isthe computer’s new effective access time? iii. How much of a speedup does the on-chip cache give the computer?
- Given a system with 2 memory channels and 4 DRAM DIMMs (2 DIMMs per channel), each DIMM has: • 1 rank per DIMM • 8 chips per rank • 8 bits per column • 8 banks per chip • 32,768 rows per bank • 2,048 columns per bank A) What is the total amount (bytes) of physical memory in the system? B) What is the minimum number of physical address bits needed to address this much memory? C) With the number of physical address bits obtained in 2), also assume • The physical address space has 1M (i.e., 1048576) pages (physical frames) Virtual addresses have 64 bits What is the maximum number of pages in the virtual address space?Compute the Average access time for memory system when the time for Main Memory is 2000 ns, the time for cache is 200 ns and hit ratio is 0.9?2. Suppose that we are given 32KB SRAM ICs and 8KB ROM ICs. We want to construct the address range for RAM to be from 00000H to 3FFFFH, and from 80000H to 8FFFFH. We also want to construct the address range for ROM to be from FC000H to FFFFFH. Show a possible address decoding circuit.
- Consider a system in which the available 32kb memory space is equally divided between EPROM and RAM. The number of reminder address busA main memory unit with a capacity of 4 megabytes is built using 1Mx 1-bit DRAM chips.Each DRAM chip has 1K rows of cells with 1K Cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit?Consider a system with 2-level cache, at 0.6 hit ratio in level 1 memory. The L1 memory is 4 times faster than L2. The average access time is increased by 40% from 50 ns. What is the percentage of change in the hit ratio?