Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) 7th edition
7th Edition
ISBN: 9780199339136
Author: Adel S. Sedra, Kenneth C. Smith
Publisher: Oxford University Press
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Chapter 14, Problem D14.5P
To determine
To design: The pull up network (PUN) for given PDN.
Also to complete the logic circuit and determine the Boolean function.
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Find the logic value (high / low) of the V0 output obtained for the V1 and V2 inputs in the circuit consisting of NMOS two mosfets. (low: between 0-2.5V; high: between 2.5-5V) The reasons for the reason (high / low) for each case should be specified in filling the table.
a) The implementation of the logic function: X = ((A' + B) (C' +D' + E') + F') G' is given
below. Complete the circuit indicating the inputs (the output is already shown). Size the devices
so that the output resistance is same as that of an inverter with an NMOS WL=2 and PMOS
WL-6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down
resistance? Show your work.
b) What are the logic functions implemented by the circuits given below. Show your work.
Vco
B
B- WL=16
WIL-8
W.L-8
WL-16I
D-
A-[WL-12
Cx2
G-WL-12
Los
B
E
D-WL-12
c) What is the function of the circuit given below? Can it store information? If yes how?
TJ TT
PROBLEM# 2:55 1 Design the simpliest CMOS logic circuit to implement
(ABC) + D. How many transistors does your logic gate required?
Chapter 14 Solutions
Microelectronic Circuits (The Oxford Series in Electrical and Computer Engineering) 7th edition
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