Explanation of Solution
Cache Addressing:
The primary storage hierarchy contains cache lines that are grouped into sets. If each set contains k lines then we say that the cache is k-way associative.
A data request has an address specifying the location of the requested data. Each cache-line sized chunk of data from the lower level can only be placed into one set. The set that it can be placed into depends on its address.
The number of cache sets is equal to the number of cache blocks divided by the number of ways of associativity.
The least significant bits are used to determine the block offset.
For example:
One needs to consider the following set associative (S, E, B, m) = (8, 4, 4, 13). The derived value will be as follows:
The Index (CI):
The block off set (CO):
The tag bit (CT):
Hence, the “2” lower bits are block offsets (CO); followed by 3 sets of bit index (CI) and the remaining bits are tag bits (CT).
The following table gives the parameters for a number of different caches and the number of cache sets(S), tag bits(t), set index bits (s) and block offset bits (b) are defined.
Cache | m | C | B | E | S | t | s | b |
1 | 32 | 1024 | 4 | 1 | 256 | 22 | 8 | 2 |
2 | 32 | 1024 | 8 | 4 | 32 | 24 | 5 | 3 |
3 | 32 | 1024 | 32 | 32 | 1 | 27 | 0 | 5 |
The values for the above table are described below:
For cache-1:
It is given that
Hence:
For cache-2:
It is given that
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Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
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- ) Consider a direct-mapped cache with 128 blocks. The block size is 32 bytes. (03) Find the number of tag bits, index bits, and offset bits in a 32-bit address. Find the number of bits required to store all the valid and tag bits in the cache. Given the following sequence of address references in decimal: 20000, 20004, 20008, 20016, 24108, 24112, 24116, 24120. Starting with an empty cache, show the index (line) and tag for each address and indicate whether a hit or a miss.arrow_forwardPlease help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?arrow_forward(d) Given memory holes (i.e., unused memory blocks) of 100K, 500K, 200K, 300K and 600K (in address order) as shown below, how would each of the first-fit, next-fit, best- fit algorithms allocate memory requests of 120K, 320K, 280K, 90K and 210K (in this order). The shaded areas are used/allocated regions that are not available. 100k 500k 200k 300k 600k Figure 2: Current status of main memoryarrow_forward
- Question 3 (Cache Memory Mapping): I (a) For the main memory address 0:0:0, briefly explain how a search is performed in two-way set associative mapping. Assume that the main memory size is 4 GB, the cache memory is 8 KB and the size of cache block is 32 bytes. (b) A 4-way set associative mapped cache consists of 64 blocks, divided into 4 sets. Main memory consists of 4K blocks, each containing 128 locations. Complete the following format for the main memory address by showing all your workings and find the tag size. [Hint: Calculate the no. of locations in the main memory, which gives the memory size in terms of the total number of bits] , Set No. Block No. Location Within Block No. of bitsarrow_forwardc) On a machine with 32-bit words and 32-bit addresses, suppose the cache is an 16MB 8-way set-associative cache, with 8-word cache lines. Indicate how an address would be partitioned into fields to allow a single word to be fetched from the cache by the CPU (just indicate what the fields are, the order of the flelds in the address, and how each field is). Show many bits your work.arrow_forward(5 points) A memory hierarchy has following hit rates and average access time (for sequential cache access) of CPU. Calculate the last hit rate. Hit Rate (%) 75 85 ??? Average Access Time of CPU (ns) 25 20 15arrow_forward
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